These Schottky-clamped high-performance multiplexers
feature 3-STATE outputs that can interface directly with
data lines of bus-organized systems. With all but one of the
common outputs disabled (at a high impedance state), the
low impedance of the single enabled output will drive the
bus line to a HIGH or LOW logic level. To minimize the pos-
sibility that two outputs will attempt to take a common bus
to opposite logic levels, the output enable circuitry is
designed such that the output disable times are shorter
than the output enable times.
This 3-STATE output feature means that n-bit (paralleled)
data selectors with up to 258 sources can be implemented
for data buses. It also permits the use of standard TTL reg-
isters for data retention throughout the system.